用verilog状态机写交通灯
//交通信号灯的控制程序
//A）红灯亮20s后黄灯亮，黄灯亮10s后绿灯亮，绿灯亮20s后黄灯亮，黄灯亮10s后红灯亮，如此循环。
//B）以led0作为红灯，led1作为黄灯，led2作为绿灯。

module  traffic_lights(
input         wire                clk,
input         wire                 rst,
output       reg   [7:0]       led
);

reg      [25:0] cnt;
localparam     T=50_000_000;

reg   [2:0] cstate;
localparam    led0=0;
localparam    led1=1;
localparam    led2=2;
localparam    led3=3;

reg   [4:0]  t=0;        //定义时间
always@(posedge clk or posedge rst) begin
if(rst)
	cnt<=0;
else if(cnt==T-1)
	cnt<=0;
else
	cnt<=cnt+1;
end

always@(posedge clk or posedge rst) begin
if(rst)	begin
	led<=8'b0000_0000;
	cstate<=0;
end
else
		case(cstate)
		         led0         :           begin
												  led<= 8'b1010_1010;           // 红灯亮
															if(t==19) begin           
													              cstate<=led1;
																  t<=0;
				                                             end
												            else  if(cnt==T-1)
																   t<=t+1;
															else
															       cstate<=led0;
																        
				                               end
		         led1         :           begin
												  led<= 8'b1111_1111;           //黄灯亮
															if (t==9) begin
													              cstate<=led2;
																  t<=0;
				                                             end
												            else  if(cnt==T-1)
																   t<=t+1;
															else
															       cstate<=led1;	        
				                               end
		         led2         :           begin
												  led<= 8'b0101_0101;          //绿灯亮
															if (t==19) begin
													              cstate<=led3;
																  t<=0;
				                                             end
												            else  if(cnt==T-1)
																   t<=t+1;
															else
															       cstate<=led2;	        
				                               end

		         led3         :           begin
												  led<= 8'b1111_1111;            //黄灯亮
															if (t==9) begin
													              cstate<=led0;
																  t<=0;
				                                             end
												            else  if(cnt==T-1)
																   t<=t+1;
															else
															       cstate<=led3;	        
				                               end
                 default      :          begin
                                                    	led<=8'b0000_0000;
                                                    	cstate<=0;
                                              end
				 endcase
end
endmodule 

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